Common receiver architectures for high-speed serial data transmission are often based on either frequency/phase tracking or over-sampling. Each of these types is discussed below.
Tracking Receivers
A tracking receiver operates by locking on to the frequency and phase of the incoming data. Frequency/phase tracking is accomplished using a feedback loop, which generates frequency and phase control signals to a clock synthesizer. A typical tracking receiver recovers the clock embedded in the incoming data. It then uses the recovered clock to sample the data bits. In the lock condition, the tracking circuit continuously aligns the local clock phase to the edges observed in the recovered waveform. The recovered data is clocked in to a First-In-First Out (FIFO) buffer, which is read out synchronously relative to a local clock.
Oversampling Receivers
In an over-sampling receiver, the input data signal is sampled at a certain multiple (e.g., three times the data rate) of the nominal data rate. The local clock is nearly equal to the speed of the transmit data clock. However, an over-sampling receiver does not require the local clock to track the transmit data clock. The input signal is sampled during periodic time windows. The resulting sample bits, which occur during multiple phases of a local clock, are re-synchronized to a single clock phase. The sampled bits are then fed to a phase selection logic, which picks the best samples for the data bits within that sampling window.
Both the tracking and over-sampling receivers have some drawbacks. Tracking receivers require analog circuits that are particularly sensitive to noise. Often, the designs of tracking receivers are large and/or need additional power to function correctly in integrated circuits that contain a large amount of high frequency digital logic circuitry. Extreme care must be taken during layout, at both the chip level and board level, for receivers that contain sensitive and unduly large analog circuits. This is due to the possibility of noise sources caused by high-speed switching occurring in the digital logic. Consequently, circuit designers employ various techniques to lessen the impact of these noise sources on the sensitive analog circuits. However these techniques often result in increased circuit costs (both in size and investment).
In general, over-sampling receivers contain a much higher percentage of digital circuitry than tracking receivers, and therefore, theoretically should be more tolerant of noise. However, the over-sampling protocol introduces an additional source of jitter, called quantization jitter, due to the uncertainty associated with the sampled data. Quantization jitter effectively reduces the system level noise margins. As the rate of over-sampling is often much faster than the data rate, the speed of the digital logic limits the overall speed of the communication process to a much lower rate than otherwise possible using a tracking receiver. As a consequence, very high-speed receivers usually employ analog phase-locked loop circuits to enable operation of the receiver close to the limit of the digital circuitry.
The invention is therefore directed to the problem of developing a method and apparatus for communicating at high speeds without introducing noise by requiring analog elements on an otherwise digital circuit